The clock uses a low-cost four-character 7-segment LED display module available from SparkFun, or Hobbytronics and Proto-PIC in the UK. Modules are also available for the DCF 77.5kHz transmitter in Frankfurt, which covers large parts of Europe, and the WWVB 60kHz transmitter near Fort Collins, Colorado, USA. The module I used receives UK time from the MSF 60kHz transmitter at Anthorn, Cumbria, and is suitable for use throughout the UK and in parts of Europe. The clock uses a radio time module available from PV Electronics which takes a 3V to 5V supply and outputs the raw timecode on a single pin:
#RADIO CLOCK CHIP CODE#
This post describes the simple radio clock I built, based on a low-cost 7-segment display and an ATtiny84:ĪTtiny84 Radio Time Code Clock. It seems such an elegant solution to providing accurate time, rather than having to maintain your own local time using a crystal or RTC module. These are transmitted in several countries, giving a time code synchronised to an atomic clock, together with summer time adjustment, the date and day of week, and information about leap seconds. Measurements of conducted spectra showed a similar result spectral energies are spread and peaks of the fundamental and harmonics were reduced by 13dB.I've always wanted to build a clock based on the radio time code signal. The reduction in EMI is around 13dB at the fundamental and third harmonic. Measurements were based on CISPR16-1, an international standard for measuring radio interference.
#RADIO CLOCK CHIP DRIVERS#
Current driven by clock and data drivers was passed through a metre of unshielded ribbon cable. The diagram shows the radiated spectra from this prototype system running with a fundamental frequency of 82MHz. The core size is 0.6 x 0.4mm and it consumes 45mW at 3V. The researchers fabricated a delay locked loop (DLL) using 0.35?m CMOS. Thus periods when the clock is either at 0? or -180? are interspersed with periods when the clock is running faster or slower. Then the process reverses and the phase is brought back to 0?. A phase of -180? is reached in about 16 clock cycles. Each consecutive edge changes the phase of the clock by 3.3 per cent of a clock period. Therefore, for best results, the system was designed to vary the phase of the clock between 0 and -180?.
EMI peaks should be reduced by 5, 13, 6 and 3dB as phase is changed by 90?, 180?, 270? and 360? respectively.
The clock signal is dithered such that its phase varies over a number of clock cycles.Ī fast Fourier transform analysis showed that different phase changes gave a variety of reductions in EMI. Seoul University’s method is called spread spectrum phase modulation (SSPM). The work is aimed at devices such as notebook computers which have high clock and data speeds, but cannot afford the weight and cost of too much shielding material. A paper at ISSCC has shown a clock dithering technique that spreads the frequency spectra of clock and data signals, and hence reduces their peaks. The tendency for high speed equipment such as handheld PCs to emit more electromagnetic interference (EMI) has been addressed by researchers at Korea’s Seoul National University. Clock dithering technique tackles chip interference Richrd Ball